基于流水化和滑动窗口结构的低功耗指令Cache设计

嵌入式处理器中Cache的应用极大地提高了处理器的性能,同时Cache,尤其是指令Cache功耗占据了处理器很大一部分功耗,关闭不必要的tag SRAM和data SRAM的访问,可以极大地降低功耗。提出了一种流水化的指令Cache访问机制,关闭不必要的data SRAM的访问;并且通过记录指令Cache行的信息和预测下一行的Cache形成一个Cache行滑动窗口,关闭不必要的tag SRAM访问。所提出的方法没有性能损失,在SMIC 90nm工艺下进行功耗分析,其指令访问的功耗降低50%。

Low power instruction cache design based on pipeline and sliding window structure

While the application of cache significantly improves the performance of the embedded processors, the cache, especially the I-cache, also consumes a large proportion of power. Reducing unnecessary accesses to the tag SRAM and the data SRAM can lower the power consumption. In this paper we design a pipeline I-Cache access mechanism that can deny the unnecessary access to the data SRAM. We also present a slide window of the cache lines by recording the information of the current introduction cache line and by predicting the information of the next cache line to reduce the unnecessary access to the tag SRAM. In the SMIC 90nm, the proposed method can achieve a 50% power reduction of the I-Cache without any performance degradation.