| 基于指令集模拟器的处理器建模与验证 |
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| 引用本文： | 严迎建,徐劲松,陈韬,刘军伟. 基于指令集模拟器的处理器建模与验证[J]. 计算机工程, 2008, 34(5): 248-250 |
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| 作者姓名： | 严迎建 徐劲松 陈韬 刘军伟 |
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| 作者单位： | 解放军信息工程大学电子技术学院,郑州,450004 |
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| 基金项目： | 国家部委基础预研基金资助项目 |
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| 摘 要： | 介绍处理器仿真建模技术以及指令集模拟器在其中的应用，讨论处理器ISA, MA模型建立以及指令精确、时钟精确的指令集模拟器实现方法，提出一种基于多线程技术的调试器集成方法，介绍指令集模拟器在一款密码专用微处理器开发过程中的具体应用方法。
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| 关 键 词： | 指令集模拟器 处理器建模 指令精确 时钟精确 流水线处理器 |
Processor Modeling and Verification Based on Instruction Set Simulator |
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| YAN Ying-jian,XU Jin-song,CHEN Tao,LIU Jun-wei. Processor Modeling and Verification Based on Instruction Set Simulator[J]. Computer Engineering, 2008, 34(5): 248-250 |
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| Authors: | YAN Ying-jian XU Jin-song CHEN Tao LIU Jun-wei |
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| Affiliation: | (Department of Information Engineering, PLA University of Information Engineering, Zhengzhou 450004) |
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| Abstract: | Instruction Set Simulator(ISS) and its application in processor modeling and verification are introduced. The modeling methods of Instruction Set Architecture(ISA) and Micro-Architecture(MA) are discussed. Furthermore, the implementation of instruction accurate and cycle accurate instruction set simulator are also investigated. Multithreading technology is used in integration of debugger with ISS. Application of ISS in development of a cipher specific processor is presented. |
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| Keywords: | Instruction Set Simulator(ISS) processor modeling instruction accurate cycle accurate pipeline processor |
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