Endurance Reliability of Multilevel-Cell Flash Memory Using a $ hbox{ZrO}_{2}/hbox{Si}_{3}hbox{N}_{4}$ Dual Charge Storage Layer

The mechanisms of programming/erasing (P/E) and endurance degradation have been investigated for multilevel-cell (MLC) Flash memories using a $hbox{Si}_{3}hbox{N}_{4}$ (NROM) or a $hbox{ZrO}_{2}/hbox{Si}_{3}hbox{N}_{4}$ dual charge storage layer (DCSL). Threshold-voltage $(V_{rm th})$ -level disturbance is found to be the major endurance degradation factor of NROM-type MLCs, whereas separated charge storage and step-up potential wells give rise to a superior $V_{rm th}$ -level controllability for DCSL MLCs. The programmed $V_{rm th}$ levels of DCSL MLCs are controlled by the spatial charge distribution, as well as the charge storage capacity of each storage layer, rather than the charge injection. As a result, DCSL MLCs show negligible $V_{rm th}$-level offsets ($ ? $ 0.2 V) that are maintained throughout the $hbox{10}^{5}$ P/E cycles, demonstrating significantly improved endurance reliability compared to NROM-type MLCs.