支持线程级猜测的存储体系结构设计

在线程级猜测中进行数据依赖相关检测时，存在Cache一致性协议无法容忍线程切换引起的Cache块替换等问题。为此，通过分析推测线程数据管理模型，结合推测线程切概率低的特点，提出一种分布-共享式恢复缓冲区结构。该结构在进行Cache一致性检验时结合作废向量和版本优先级寄存器进行数据依赖检测，利用L2 Cache进行推测数据缓冲和恢复以支持推测线程切换。修改SESC模拟器以验证和评估该存储体系结构。实验结果表明，在保持模拟器理想加速比的情况下，该存储体系结构可以较好地支持推测线程切换。

Design of Memory Architecture with Thread-level Speculation Support

In order to remove the restrictions that the global arbiter is hard to implement and Thread-level Speculation(TLS) runtime can not swap speculative threads out of their host processors when using Cache coherence protocol. By analyzing the speculative data management policy in TLS, it is found that the buffer for modified data for each speculative thread is small and the possibility of speculative threads being swapped out of their host cores is so small that can be neglected. This paper designs a shared-distributed memory system. The proposed memory system uses invalidation vectors and speculation version priority registers for data dependence checking when doing cache coherence checking. A flat of memory in the L2 Cache is reserved to buffer and restore the data modified by the speculative threads, which makes speculative swapping possible. The paper modifies the SESC simulator to confirm the performance and correctness of the proposed memory system. Experimental results show that when keeping the ideal speedups, the proposed memory system can support speculative thread swapping very well.