Effect of Time Lag in Response to Switching Signal in Interrupted Electric Circuit

In this study, we analyze the characteristics of an interrupted electric circuit. In particular, we focus on a special situation where the switching action of the circuit is delayed because of a time lag in the response to the switching signal. This situation is observed in switching circuits driven by a high-frequency switching signal. However, the fundamental characteristics of this type of circuit have not yet been clarified. To address this shortfall, we assume that a time lag of the response to the switching signal occurs in simple interrupted electric circuits, and investigate how this time lag affects circuit characteristics. First, we show the model of a circuit whose switching action is the same as that of a current-mode-controlled dc/dc converter. Here by using logic circuits, we impose an artificial time lag on the response to the switching signal. Next, we define a sampled data model (i.e., a return map) that we analyze in detail. Based on the return map, we derive one- and two-parameter bifurcation diagrams. Finally, we compare the bifurcation diagrams constructed with time lag to those constructed without time lag. The results clearly show that time lag is responsible for a new structure in the return map that does not occur in circuits with ideal switching. This new return map structure is a key to understanding the essential characteristics of circuits with time lag. Furthermore, the mathematical results are verified experimentally.