A room temperature 0.1 μm CMOS on SOI |
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| Authors: | Shahidi G.G. Anderson C.A. Chappell B.A. Chappell T.I. Comfort J.H. Davari B. Dennard R.H. Franch R.L. McFarland P.A. Neely J.S. Ning T.H. Polcari M.R. Warnock J.D. |
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| Affiliation: | Semicond. Res. & Dev. Center, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY; |
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| Abstract: | An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, CL=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained |
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