| 基于扫描链的FPGA可编程逻辑模块测试 |
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| 引用本文： | 周发标,杨海钢,秋小强,李凡阳,王飞.基于扫描链的FPGA可编程逻辑模块测试[J].微电子学与计算机,2012,29(2):48-53. |
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| 作者姓名： | 周发标 杨海钢 秋小强 李凡阳 王飞 |
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| 作者单位： | 1. 中国科学院电子学研究所可编程芯片与系统研究室,北京100190／中国科学院研究生院,北京100049
2. 中国科学院电子学研究所可编程芯片与系统研究室,北京,100190 |
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| 摘 要： | 随着FPGA规模的不断增大和结构的日益复杂,FPGA的测试也变得越来越困难.由此提出了一种可配置的FPGA芯核扫描链设计,并讨论了基于扫描链的可编程逻辑模块（Configuration Logic Blocks CLB）测试.提出的扫描设计可以通过配置调整扫描链的构成,从而能够处理多个寄存器故障,且在有寄存器故障发生时,重新配置后能继续用于芯片的测试.基于扫描链的CLB测试,以扫描链中的寄存器作为CLB测试的可控制点和可观测点,降低了对连线资源的需求,可以对所有的CLB并行测试,在故障测试的过程中实现故障CLB的定位,与其它方法相比,所需配置次数减少50%以上.
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| 关 键 词： | FPGA CLB 故障测试 测试配置 |
A Fault Test and Diagnosis Method of FPGA Configurable-Logic-Blocks Based on Scan Chain |
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| ZHOU Fa-biao,YANG Hai-gang,QIU Xiao-qiang,LI Fan-yang,WANG Fei.A Fault Test and Diagnosis Method of FPGA Configurable-Logic-Blocks Based on Scan Chain[J].Microelectronics & Computer,2012,29(2):48-53. |
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| Authors: | ZHOU Fa-biao YANG Hai-gang QIU Xiao-qiang LI Fan-yang WANG Fei |
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| Affiliation: | 1(1 System on Programmable Chip Research Department,Institute of Electronics, Chinese Academy of Sciences,Beijing 100190,China; 2 Graduate University of the Chinese Academy of Sciences,Beijing 100049,China) |
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| Abstract: | This paper presents a configurable scan-chain design in FPGA and a test method for Configurable Logic Blocks(CLB) based on scan chain.The proposed scan-chain design can test multiple register faults by configure the register in scan chain.The test method based on scan-chain can test all CLBs in parallel and diagnose fault CLB during fault test process,so it reduces the configuration numbers need for fault test and diagnosis.Compare with the other methods the proposed method can reduce test configuration times more than 50% and diagnosis fault CLB in test process. |
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| Keywords: | FPGA CLB Fault Test Test Configuration |
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