| 采样可选择的FPGA片内逻辑分析仪设计方法 |
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| 引用本文： | 谭宜涛,杨海钢,周发标,张茉莉,路宝珠. 采样可选择的FPGA片内逻辑分析仪设计方法[J]. 微电子学与计算机, 2012, 29(2): 59-64 |
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| 作者姓名： | 谭宜涛 杨海钢 周发标 张茉莉 路宝珠 |
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| 作者单位： | 1. 中国科学院电子学研究所可编程芯片与系统研究室,北京100190／中国科学院研究生院,北京100190
2. 中国科学院电子学研究所可编程芯片与系统研究室,北京,100190 |
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| 摘 要： | 针对大容量的信号采样时片内逻辑分析仪存储器资源紧张的情况,本文提出了一种采样可选择的FPGA片内逻辑分析仪的设计方法.本方法通过布局布线约束实现JTAG硬核的复用,并利用JTAG硬核修改FPGA内寄存器实现采样信号的重新选择.测试结果表明,与某商用工具相比,根据该方法实现的片内逻辑分析仪对采样信号进行N分组后,在同等条件下所需的片内存储资源降低到1/N,同时设计时序的稳定性得以保证.
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| 关 键 词： | FPGA 片内逻辑分析仪 JTAG硬核 采样可选择 |
Design of an Sampling Selectable FPGA Embedded Logic Analyzer |
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| TAN Yi-tao,YANG Hai-gang,ZHOU Fa-biao,ZHANG Mo-li,LU Bao-zhu. Design of an Sampling Selectable FPGA Embedded Logic Analyzer[J]. Microelectronics & Computer, 2012, 29(2): 59-64 |
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| Authors: | TAN Yi-tao YANG Hai-gang ZHOU Fa-biao ZHANG Mo-li LU Bao-zhu |
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| Affiliation: | 1(1 System on Programmable Chip Research Department,Institute of Electronics, Chinese Academy of Sciences,Beijing 100190,China; 2 Graduate University of the Chinese Academy of Sciences,Beijing 100190,China) |
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| Abstract: | This paper proposes a design method of FPGA embedded logic analyzer for large storage in which the sample signals can be reselected.In this method,the JTAG hard core can be reused by constraining the placement and routing,and the sample signals can be reselected by changing the configurable registers via JTAG hard core.According to the measurement results,compared with the commercial tools,the demand of the embedded RAM resource can be reduced to the amount of 1/N which N equals the number of the sample groups,and the timing stability can be kept in observing the different signals. |
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| Keywords: | FPGA embedded logic analyzer JTAG hard core Sample Selectable |
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