| 专用集成电路静态时序分析 |
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| 引用本文： | 唐拓,张伟. 专用集成电路静态时序分析[J]. 微处理机, 2012, 33(2): 17-18,22 |
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| 作者姓名： | 唐拓 张伟 |
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| 作者单位： | 中国电子科技集团公司第四十七研究所,沈阳,110032 |
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| 摘 要： | 随着制程进入深亚微米时代,芯片设计和片上系统(SoC)设计越来越复杂,此一趋势使得如何确保IC质量成为目前所有设计从业人员不得不面临的重大课题。简单介绍了静态时序分析的基础概念及其在IC设计流程中的应用。
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| 关 键 词： | 专用集成电路设计 设计约束 静态时序分析 |
The Overview of Static Timing Analysis in ASICs |
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| TANG Tuo , ZHANG Wei. The Overview of Static Timing Analysis in ASICs[J]. Microprocessors, 2012, 33(2): 17-18,22 |
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| Authors: | TANG Tuo ZHANG Wei |
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| Affiliation: | (The 47th Research Institute of China Electronics Technology Group Corporation,Shenyang 110032,China) |
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| Abstract: | Chip design and SoC design is becoming more and more complex with the development of manufacturation into deep submicron,which makes how to ensure the quality of IC is a very important subject that has to be faced by all the designers.The basics of static timing analysis and its use in the IC design flow are introduced. |
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| Keywords: | ASIC Design Design Constraint Static Timing Analysis |
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