| CMOS模拟集成电路版图设计 |
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| 引用本文： | 解放,罗闯. CMOS模拟集成电路版图设计[J]. 微处理机, 2012, 33(3): 4-6 |
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| 作者姓名： | 解放 罗闯 |
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| 作者单位： | 中国电子科技集团公司第四十七研究所,沈阳,110032 |
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| 摘 要： | 由于模拟集成电路的性能与版图设计密切相关,着重介绍了CMOS模拟电路版图设计的一般思路,优化器件结构和平面布局使寄生效应对电路性能的影响降至最低。
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| 关 键 词： | 模拟电路 版图设计 寄生电容 |
Layout Design for CMOS Analog Circuit |
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| XIE Fang , LUO Chuang. Layout Design for CMOS Analog Circuit[J]. Microprocessors, 2012, 33(3): 4-6 |
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| Authors: | XIE Fang LUO Chuang |
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| Affiliation: | (The 47th Research Institute of China Electronics Technology Group Corporation,Shenyang 110032,China) |
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| Abstract: | Because the performance of analog circuit have great relationship with layout design,common consideration about layout design of CMOS analog circuit is introduced.Optimization of device structure and plane floorplan degrade the effect of parasitical to the minimum for circuit performance. |
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| Keywords: | Analog circuit Layout design Parasitic capacitance |
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