| 一种高速只读存储器拓扑结构的设计 |
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| 引用本文： | 陈奕含,罗前,陈志钧,罗小勇,李平. 一种高速只读存储器拓扑结构的设计[J]. 微电子学, 2012, 42(1): 46-49 |
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| 作者姓名： | 陈奕含 罗前 陈志钧 罗小勇 李平 |
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| 作者单位： | 电子科技大学电子薄膜与集成器件国家重点实验室,成都,610054 |
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| 基金项目： | 电子薄膜与集成器件国家重点实验室创新基金 |
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| 摘 要： | 随着只读存储器密度越来越大,对读取速度的要求越来越高,位线大电容逐渐成为影响只读存储器读取速度的关键问题.设计了一种存储器拓扑结构,这种结构通过改变存储单元读取点的位置,能有效避免位线大电容充放电对读取速度的不利影响,极大地缩短了读取周期,提高了只读存储器的读取速度.该拓扑结构的优势在TSMC 0.13μm工艺仿真库里得到验证.
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| 关 键 词： | 只读存储器 位线电容 拓扑结构 |
Design of Topology of a High-Speed ROM |
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| CHEN Yihan , LUO Qian , CHEN Zhijun , LUO Xiaoyong , LI Ping. Design of Topology of a High-Speed ROM[J]. Microelectronics, 2012, 42(1): 46-49 |
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| Authors: | CHEN Yihan LUO Qian CHEN Zhijun LUO Xiaoyong LI Ping |
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| Affiliation: | (State Key Lab of Electronic Thin Films and Integrated Devices,Univ.of Elec.Sci.& Technol.of China,Chengdu 610054,P.R.China) |
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| Abstract: | With increasing density of read-only memories(ROM) and high speed demand for read-out process,large bit-line capacitance is becoming critical for ROM to achieve high-speed.A topology of read-only memory was designed,which could avoid negative effects of the large capacitance on read-out speed by adjusting read point of the memory cell,thus significantly reducing the reading cycle of the sense amplifier,and improving reading speed of read-only memory.The proposed topology was validated by simulations based on TSMC 0.13 μm model. |
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| Keywords: | Read-only memory Bit-line capacitance Topology |
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