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Searching for Global Test Costs Optimization in Core-Based Systems
Authors:Érika Cota  Luigi Carro  Marcelo Lubaszewski  Alex Orailoğlu
Affiliation:(1) PPGC—Instituto de Informática, Universidade Federal do Rio Grande do Sul, P.O. Box, 15064, Porto Alegre, 91501-970, Brazil;(2) PPGEE—Electrical Engineering Department and PPGC—Instituto de Informática, Universidade Federal do Rio Grande do Sul, Av. Osvaldo Aranha, 103, Porto Alegre, 90035-190, Brazil;(3) Computer Science and Engineering Department, University of California, San Diego, La Jolla, CA 92093, USA
Abstract:This paper proposes a comprehensive model for test planning and design space exploration in a core-based environment. The proposed approach relies on the reuse of available system resources for the definition of the test access mechanism, and for the optimization of several cost factors (area overhead, pin count, power constraints and test time). The use of an expanded test access model and its concurrent definition with the system test schedule makes it possible the search for a cost effective global solution. Experimental results over the ITC'02 SOC Test Benchmarks show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test planning.
Keywords:SOC testing  embedded cores testing  design for test  design space exploration
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