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0.18 μm CMOS高效高增益功率放大器设计
引用本文:张海鹏,汪洋,李浩.0.18 μm CMOS高效高增益功率放大器设计[J].杭州电子科技大学学报,2012,32(5):9-12.
作者姓名:张海鹏  汪洋  李浩
作者单位:杭州电子科技大学电子信息学院,浙江杭州,310018
基金项目:863计划资助项目(AA09Z239); 浙江省科技计划资助项目(C21G2040066)
摘    要:在自偏置A类共源共栅射频功率放大电路拓扑基础上,基于SMIC 0.18 μm CMOS工艺设计了两级自偏置A类射频功率放大器电路.该射频功率放大器电路采用两级共源共栅结构,在共栅MOS管上采用自偏置.采用Cadence公司的SpectreRF工具对电路进行仿真与优化.设计与优化结果表明,在2.4GHz频率下,输出功率为20.3dBm,功率附加效率为49%,功率增益达到32dB.

关 键 词:功率放大器  自偏置  共源共栅

0.18m CMOS Power Amplifier with High Efficiency and High Gain
ZHANG Hai-peng , WANG Yang , LI Hao.0.18m CMOS Power Amplifier with High Efficiency and High Gain[J].Journal of Hangzhou Dianzi University,2012,32(5):9-12.
Authors:ZHANG Hai-peng  WANG Yang  LI Hao
Affiliation:(School of Electronics Information,Hangzhou Dianzi University,Hangzhou Zhejiang 310018,China)
Abstract:Based on the self-biased cascode circuit topology of the class-A RF power amplifier,a two-stage class-A RF power amplifier was designed in 0.18 m CMOS technology.This power amplifier consists of two-stage cascode architecture with self-biased adopted for the CG MOS transistors.Cadence SpectreRF was used to simulate and optimize the designed circuit.The results indicate that the output power of the amplifier is 20.3dBm,the power added efficiency is 49%,and the small signal power gain of the circuit reaches 32dB at the frequency of 2.4GHz.
Keywords:power amplifier  self-biased  cascode
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