基于MIPS指令集的超标量和超长指令字混合架构处理器设计

针对嵌入式和移动设备对处理器高性能低功耗日趋强烈的要求，提出一种基于MIPS指令集的顺序超标量和超长指令字混合架构处理器设计方案，便于以同构多核架构代替目前业界普遍采用的CPU与DSP异构结构，降低功耗面积，同时以VLIW模式获得较好的DSP性能。在PD（Processor Designer）平台下以LISA语言建立处理器的周期精度软件模拟器，通用性能和DSP性能分别由dhrystone、coremark基准测试程序及EEMBC的telecom测试程序进行验证。测试结果表明该设计以较低的硬件开销通过混合架构获得较高的数字信号处理性能，在高性能低功耗的处理器应用场景中拥有良好的适用性。

Design of Superscalar/VLIW Hybrid Processor Based on MIPS Instruction Set

In order to reduce the area and power consumption of processor, this paper proposed a hybrid architecture of Superscalar/VLIW based on MIPS instruction set. Requirements of DSP to mobile and embedded devices are becoming higher and higher, data controling and data processing are realized by the CPU and DSP heterogeneous structure which is widespread used. The hybrid architecture processor has the functionality of general-purpose processor, which can improve DSP performance with VLIW. The paper has described and verified the design by LISA and PD, tested the generality performance through dhrystone and coremark, the DSP performance through EEMBC-telecom. The test results demonstrate that the hybrid architecture processor can run the general program of MIPS instruction set, and it has high performance of digital signal processing in the VLIW mode. The design has good applicability in the high performance and low power consumption application.