An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform |
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| Authors: | Shrutisagar Chandrasekaran Abbes Amira Shi Minghua Amine Bermak |
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| Affiliation: | (1) Electronic and Computer Engineering, School of Engineering and Design, Brunel University, Howell Building (H-254), West London, UK;(2) Department of Electrical and Electronic Engineering Hong Kong, University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong |
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| Abstract: | In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on
a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is
presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p
2), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations
are carried out to analyse the performance of the FRIT core developed.
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| Keywords: | Finite Ridgelet Transform Finite Radon Transform Wavelets FPGA VLSI ASIC Image processing |
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