Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer

The simultaneous improvement in the erase and retention characteristics in a TANOS $(hbox{TaN}{-}hbox{Al}_{2}hbox{O}_{3}{-}hbox{Si}_{3}hbox{N}_{4}{-}break hbox{SiO}_{2}{-}hbox{Si})$ Flash memory transistor by utilizing the band-engineered and compositionally graded $hbox{SiN}_{x}$ trap layer is demonstrated. With the process optimizations, a $? hbox{4}$ V memory window and excellent 150 $^{circ}hbox{C}$ 24-h retention (0.1–0.5 V charge loss) for a programmed $Delta V_{t} = hbox{4} hbox{V}$ with respect to the initial state are obtained. The band-engineered $hbox{SiN}_{x}$ charge storage layer enables Flash scaling beyond the floating-gate technology with a promise for improved erase speed, retention, lower supply voltages, and multilevel cell applications.