| 基于FPGA的线性卷积的实时实现 |
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| 引用本文： | 范海波. 基于FPGA的线性卷积的实时实现[J]. 电子科技, 2010, 23(5): 58-62 |
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| 作者姓名： | 范海波 |
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| 作者单位： | 黑龙江工商职业技术学院信息工程系,黑龙江哈尔滨,150080 |
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| 摘 要： | 从实际工程应用出发,研究了在基于FPGA上快速傅里叶变换实现线性卷积的方法,并搭建了一个基于Altera 的EP2S60硬件处理平台,利用Altera提供的FFT IP核,在100 MHz系统时钟下,数据吞吐率可达100 Ms/s。
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| 关 键 词： | 快速傅里叶变换 卷积 现场可编程门阵列 |
Real-time Implementation of Linear Convolution Based on FPGA |
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| Fan Haibo. Real-time Implementation of Linear Convolution Based on FPGA[J]. Electronic Science and Technology, 2010, 23(5): 58-62 |
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| Authors: | Fan Haibo |
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| Affiliation: | (Department of Imformation Engnieering,Heilongjiang Province Industry and Commercial Vocational Technical College,Harbin 150080,China) |
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| Abstract: | An implementation of fast computing linear convolution based on Fast Fourier Transform is proposed. With the hardware plant based on the Ahera＇s EP2S60, the throughput of the whole system with Ahera＇s FFT IP core is as high as 100 Msps under the 100 MHz system clock. |
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| Keywords: | FFT convolution FPGA |
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