FPGA implementation of reversible watermarking in digital images using reversible contrast mapping |
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| Affiliation: | 1. Department of Electronics and Comm. Engineering, College of Engineering and Management, Kolaghat 721171, India;2. Department of Information Technology, Indian Institute of Engineering Science & Technology, Shibpur, Howrah 711103, India;1. School of Electrical Engineering, Korea University, Anam-Dong 5-Ga, Sungbuk-Gu, Seoul 136-701, South Korea;2. College of Automation, Harbin University of Engineering, Harbin, Heilongjiang, 150001, China;3. School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, SA 5005, Australia;1. Department of Electrical Engineering, PIEAS, Islamabad, Pakistan;2. Department of Electrical Engineering, COMSATS Institute of Information Technology, Islamabad, Pakistan;1. Department of Epidemiology, University of Iowa College of Public Health, 145 N Riverside Drive, Iowa City, IA 52242, USA;2. VA Center for Comprehensive Access and Delivery Research and Evaluation (CADRE), Iowa City VA Health Care System, Iowa City, IA, USA;3. Department of Nursing, VA Medical Center, Memphis, TN, USA;4. Division of Colon and Rectal Surgery, Department of Surgery, University of South Florida, Tampa, FL, USA;5. Division of Gastrointestinal Surgery, Minimally Invasive and Bariatric Surgery, Department of Surgery, University of Iowa College of Medicine, Iowa City, IA, USA;1. School of Electronics and Information, Jiangsu University of Science and Technology, Zhenjiang 212003, PR China;2. School of Automation, Nanjing University of Science and Technology, Nanjing 210094, PR China;1. Shanghai Key Lab of Modern Optical System, Department of Control Science and Engineering, University of Shanghai for Science and Technology, Shanghai 200093, China;2. Department of Mathematics, Yangzhou University, Yangzhou 225002, China.;3. Communication Systems and Networks (CSN) Research Group, Faculty of Engineering, King Abdulaziz University, Jeddah 21589, Saudi Arabia;4. Informatization Office, University of Shanghai for Science and Technology, Shanghai 200093, China |
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| Abstract: | Reversible contrast mapping (RCM) and its various modified versions are used extensively in reversible watermarking (RW) to embed secret information into the digital contents. RCM based RW accomplishes a simple integer transform applied on pair of pixels and their least significant bits (LSB) are used for data embedding. It is perfectly invertible even if the LSBs of the transformed pixels are lost during data embedding. RCM offers high embedding rate at relatively low visual distortion (embedding distortion). Moreover, low computation cost and ease of hardware realization make it attractive for real-time implementation. To this aim, this paper proposes a field programmable gate array (FPGA) based very large scale integration (VLSI) architecture of RCM-RW algorithm for digital images that can serve the purpose of media authentication in real-time environment. Two architectures, one for block size (8 × 8) and the other one for (32 × 32) block are developed. The proposed architecture allows a 6-stage pipelining technique to speed up the circuit operation. For a cover image of block size (32 × 32), the proposed architecture requires 9881 slices, 9347 slice flip-flops, 11291 number 4-input LUTs, 3 BRAMs and a data rate of 1.0395 Mbps at an operating frequency as high as 98.76 MHz. |
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| Keywords: | Reversible watermarking Reversible contrast mapping FPGA |
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