Circulating current elimination scheme for parallel operation of common dc bus inverters

In this paper, a circulating current elimination scheme for common dc bus parallel inverter system is proposed. A dead-time elimination sinusoidal pulse width modulation (SPWM) is presented to overcome the circulating current caused by dead-time effects. The circulating current elimination scheme combines dead-time elimination SPWM and double loop control method, which is compose of an outer voltage loop and an inner current loop. Synchronizing the pulse width modulation (PWM) signals of each parallel unit, the instantaneous output PWM voltages of the parallel units can be kept the same, apart from the zero crossing of load current. The proposed scheme is easy to be implemented on the digital control board using digital signal processing (DSP) and field-programmable gate array (FPGA). Experimental results are depicted to demonstrate the validity and features of the proposed circulating current elimination scheme.