Power-aware code scheduling assisted with power gating and DVS |
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| Affiliation: | 1. University of Lille, France;2. Universidad de la República, Uruguay;3. The University of Sydney, Australia;4. University of Luxembourg, Luxembourg;1. Department of Hematology, Oncology and Transplantation, University of Minnesota, Minneapolis, MN 55455, USA;2. Section of Medical Oncology, Department of Medicine, UAB Comprehensive Cancer Center, 1802 6th Avenue South, NP2540B, Birmingham, AL 35294, USA;1. Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, 200050, China;2. School of Information Science and Technology, ShanghaiTech University, Shanghai, 201210, China;3. University of Chinese Academy of Sciences, Beijing, 100049, China;4. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310058, China |
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| Abstract: | Traditionally, code scheduling is used to optimize the performance of an application, because it can rearrange the code to allow the execution of independent instructions in parallel based on instruction level parallelism (ILP). According to our observations, it can also be applied to reduce power dissipation by taking advantage of the properties of existing low-power techniques. In this paper, we present a power-aware code scheduling (PACS), which is a code scheduling integrated with power gating (PG) and dynamic voltage scaling (DVS) to reduce power consumption while executing an application. In other words, from the viewpoint of compilation optimization, PG and DVS can be applied simultaneously to a code and their impact can be enhanced by code scheduling to further save power. The result shows that when compared with hardware power gating, the proposed PACS can outperform by more than 33% and 41% in terms of energy delay product and energy delay2 product for DSPStone and Mediabench. |
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| Keywords: | DVS Power gating Code scheduling Compiler |
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