A Systolic Architecture and Implementation of Feedback Network for Blind Source Separation

Blind source separation of independent sources from their convolutive mixtures is a problem in many real-world multi-sensor applications. However, the existing BSS architectures are more often than not based upon software and thus not suitable for direct implementation on hardware. The existing software of feedback network algorithm is not suitable for real-time implementations. In this paper, we present a parallel algorithm and architecture for hardware implementation of blind source separation. The algorithm is based on feedback network and is highly suited for parallel processing. The implementation is designed to operate in real time for speech signal sequences. It is systolic and easily scalable by simple adding and connecting chips or modules. In order to verify the proposed architecture, we have also designed and implemented it in a hardware prototyping with Xilinx FPGAs running at 33 MHz.

H. JeongEmail: Email: