| 一种用于高速流水线ADC的时钟管理器 |
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| 引用本文： | 周小康,王继安,庞世甫,李威,龚敏.一种用于高速流水线ADC的时钟管理器[J].电子与封装,2007,7(3):20-23,37. |
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| 作者姓名： | 周小康 王继安 庞世甫 李威 龚敏 |
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| 作者单位： | 1. 四川大学物理科学与技术学院微电子技术四川省重点实验室,成都,610064
2. 电子科技大学微电子与固体电子学院,成都,610054 |
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| 摘 要： | 文章设计了一种用于高速流水线ADC的时钟管理器,该电路以延迟锁相环(DLL)电路为核心,由偏置电路、时钟输入电路、50%占空比稳定电路和无交叠时钟电路构成。该电路用0.35μmBiCMOS工艺条件下cadence spectre仿真。由测量结果可知,时钟管理器可以实现70MHz~300MHz有效输出。在250MHz典型频率下测得峰值抖动为16ps,占空比为50%,功耗为47mW。仿真结果表明该时钟管理器具有高速度、高精度、低功耗的特点,适用于高速流水线ADC。
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| 关 键 词： | 流水线ADC 50%占空比 延迟锁相环 无交叠时钟 |
| 文章编号： | 1681-1070（2007）03-0020-04 |
| 收稿时间： | 2007-01-05 |
| 修稿时间： | 2007年1月5日 |
A Clock Management Circuit in High-Speed Pipeline ADC |
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| ZHOU Xiao-kang,WANG Ji-an,PANG Shi-fu,LI Wei,GONG Min.A Clock Management Circuit in High-Speed Pipeline ADC[J].Electronics & Packaging,2007,7(3):20-23,37. |
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| Authors: | ZHOU Xiao-kang WANG Ji-an PANG Shi-fu LI Wei GONG Min |
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| Abstract: | A kind of clock management circuit, which used in high-speed pipeline ADC, was designed. The clock management circuit with DLL as its core cell consists of bias circuit, clock input circuit, 50% duty-cycle stabiliz- ing circuit and no-overlap output circuit. The circuit is based on a 0.35μm Bi CMOS process. The measured results have shown the DLL exhibits a lock range of 70MHz~300MHz while the peak-to-peak jitter, duty-cycle and power dissipation is 16ps, 50% and 47mW at 250MHz. That is, this clock management circuit has the characteristics with high speed, good precision and low power dissipation. It’s suitable for the high-speed pipeline A/D converter. |
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| Keywords: | pipeline ADC 50%duty-cycle delay-locked loop no-overlapping clock |
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