Scheme for reducing size of coefficient memory in FFT processor

Long fast Fourier transforms (FFTs) are required in applications such as orthogonal frequency division multiplexing, radars and sonars. It is highly desirable to reduce the size and power requirements of the FFT so as to realise single chip long FFT-based systems targeting portable applications. Presented here is a novel technique to reduce the coefficient memory almost by a factor of four by exploiting the relationships among the coefficient values thereby significantly reducing the area and power requirements of the hardware