| 基于FPGA的DDS基本信号发生器的设计 |
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| 引用本文： | 赵丽娜,郭宝增,刘少鹏,马韬. 基于FPGA的DDS基本信号发生器的设计[J]. 电子设计工程, 2012, 20(12): 190-192 |
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| 作者姓名： | 赵丽娜 郭宝增 刘少鹏 马韬 |
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| 作者单位： | 河北大学电子信息工程学院,河北保定,071002 |
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| 摘 要： | 本设计基于DDS原理和FPGA技术按照顺序存储方式,将对正弦波、方波、三角波、锯齿波四种波形的取样数据依次全部存储在ROM波形表里,通过外接设备拨扭开关和键盘控制所需波形信号的输出,最终将波形信息显示在LCD液晶显示屏上。各硬件模块之间的协调工作通过嵌入式软核处理器NiosⅡ用编程实现控制。本设计所搭建的LCD12864控制器是通过编程实现的IP核。
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| 关 键 词： | DDS FPGA技术 顺序存储 NiosⅡ IP核 |
Design of DDS basic signal generator based on FPGA |
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| ZHAO Li-na,GUO Bao-zeng,LIU Shao-peng,MA Tao. Design of DDS basic signal generator based on FPGA[J]. Electronic Design Engineering, 2012, 20(12): 190-192 |
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| Authors: | ZHAO Li-na GUO Bao-zeng LIU Shao-peng MA Tao |
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| Affiliation: | (College of Electronic and Informational Engineering,Hebei University,Baoding 071002,China) |
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| Abstract: | The design is based on the DDS theory and FPGA technology.According to sequence of storage ways,we put all the sampling data of sine wave,square wave,triangle wave,and sawtooth wave in ROM waveform list.By controlling the switch and the the keyboard of external equipment,we achieve the output of the waveform needed.Eventually,the information of the waveform displays in the LCD screen.Embedded soft processor NiosⅡ program to control the coordination of each hardware module.The LCD 12864 controller in this design is an IP core realized by programming. |
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| Keywords: | DDS FPGA technology sequence of storage ways Nios II IP core |
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