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| 一种单端10-bit SAR ADC IP核的设计 | |
| 引用本文： | 李靖,余昭杰,高榕,王富昕,杨小天. 一种单端10-bit SAR ADC IP核的设计[J]. 电子设计工程, 2012, 20(13): 138-141 |
| 作者姓名： | 李靖 余昭杰 高榕 王富昕 杨小天 |
| 作者单位： | 1. 吉林大学电子科学与工程学院集成光电子学国家重点联合实验室吉林大学实验区,吉林长春,130012 2. 吉林大学计算机科学与技术学院,吉林长春,130012 3. 吉林省建筑工程学院,吉林长春,130118 |
| 摘 要： | 本设计通过采用分割电容阵列对DAC进行优化,在减小了D/A转换开关消耗的能量、提高速度的基础上,实现了一款采样速度为1 MS/s的10-bit单端逐次逼近型模数转换器。使用cadence spectre工具进行仿真,仿真结果表明,设计的D/A转换器和比较器等电路满足10-bit A/D转换的要求,逐次逼近A/D转换器可以正常工作。 |
| 关 键 词： | D/A转换器 逐次逼近 低功耗 单端 二进制加权电容 |
Design of a 10 bit single-ended SAR ADC UP core |
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| LI Jing,YU Zhao-jie,GAO Rong,WANG Fu-xin,YANG Xiao-tian. Design of a 10 bit single-ended SAR ADC UP core[J]. Electronic Design Engineering, 2012, 20(13): 138-141 | |
| Authors: | LI Jing YU Zhao-jie GAO Rong WANG Fu-xin YANG Xiao-tian |
| Affiliation: | 1.College of Electronic Science and Engineering,Jilin University,Changchun 130012,China; 2.College of Computer Science and Technology,Jilin University,Changchun 130012,China; 3.Jilin Institute of Architecture and Civil Engineering,Changchun 130118,China) |
| Abstract: | A 10-bit-1-MS/s single-ended successive approximation register(SAR) analog-to-digital converter(ADC) that uses a split capacitor array to optimize the digital-to-analog converter(DAC) is presented,increase speed and reduce switching energy when the digital signal to analog signal converting.The simulation results which use the cadence spectre show that the proposed digital-to-analog converter,comparator and other circuits meet the requirements of the 10-bit analog-to-digital converter.the successive approximation register analog-to-digital converter can work successfully. |
| Keywords: | Digital-to-Analog converter successive approximation low power single-ended binary weighted capacitors |
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