| 平方根升余弦滤波器的设计与FPGA实现 |
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| 引用本文： | 山蕊,蒋林,杜慧敏.平方根升余弦滤波器的设计与FPGA实现[J].西安邮电学院学报,2011,16(3):30-33. |
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| 作者姓名： | 山蕊 蒋林 杜慧敏 |
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| 作者单位： | 1. 西安邮电学院,计算机学院,陕西,西安710121
2. 西安邮电学院,电子工程学院,陕西,西安710121 |
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| 摘 要： | 为了提高平方根升余弦滤波器的性能,采用FPGA技术,基于CSD编码和分布式计算两种算法,分别提出相应的硬件电路设计,并在QuartusⅡ综合器中进行综合.结果显示采用分布式计算算法实现的平方根升余弦滤波器性能优于CSD编码方式.
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| 关 键 词： | 平方根升余弦滤波器 CSD编码 分布式算法 FPGA |
Two Square-Root raised cosine filter based on FPGA |
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| SHAN Rui,JIANG Lin,DU Hui-min.Two Square-Root raised cosine filter based on FPGA[J].Journal of Xi'an Institute of Posts and Telecommunications,2011,16(3):30-33. |
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| Authors: | SHAN Rui JIANG Lin DU Hui-min |
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| Affiliation: | SHAN Rui1,JIANG Lin2,DU Hui-min2(1.School of Computer Science and Technology,Xi'an University of Posts and Telecommunications,Xi'an 710121,China,2.School of Electronic Engineering,China) |
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| Abstract: | To improve the quality of a square-root raised cosine filter,two hardware circuits are designed with FPGA technology.They are respectively based on CSD coding method and distributed algorithm.Synthesizing the two circuits in QuartusII shows that,the circuit based on distributed algorithm works better than that based on CSD coding method. |
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| Keywords: | square-root raised cosine filter CSD code distributed arithmetic FPGA |
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