A digit-serial multiplier for finite field GF(2/sup m/) |
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Authors: | Chang Hoon Kim Chun Pyo Hong Soonhak Kwon |
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Affiliation: | Dept. of Comput. & Inf. Eng., Daegu Univ., Kyungsan, South Korea; |
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Abstract: | In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2/sup m/) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data come in continuously, the proposed array can produce multiplication results at a rate of one every /spl lceil/m/L/spl rceil/ clock cycles, where L is the selected digit size. Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation. |
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