| 1.25Gbps串并并串转换接收器的低抖动设计 |
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| 引用本文： | 刘玮,肖磊,杨莲兴.1.25Gbps串并并串转换接收器的低抖动设计[J].固体电子学研究与进展,2009,29(1). |
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| 作者姓名： | 刘玮 肖磊 杨莲兴 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室,上海,201203 |
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| 摘 要： | 对1.25Gbps应用于千兆以太网的低抖动串并并串转换接收器进行了设计,应用了带有频率辅助的双环时钟数据恢复电路,FLL扩大了时钟数据恢复电路的捕捉范围。基于三态结构的鉴频鉴相从1.25Gbps非归零数据流中提取时钟信息,驱动一个三级的电流注入环形振荡器产生1.25GHz的低抖动时钟。从低抖动考虑引入了均衡器。该串并并串转换接收器采用TSMC0.35μm2P3M3.3V/5V混合信号CMOS技术工艺。测试结果表明了输出并行数据有较好的低抖动性能:1σ随机抖动(RJ)为7.3ps,全部抖动(TJ)为58mUI。
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| 关 键 词： | 低抖动 时钟数据恢复电路 压控振荡器 双环 鉴相器 串并并串转换 |
Low Jitter Design for 1.25 Gbps SerDes Receiver |
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| LIU Wei,XIAO Lei,YANG Lianxing.Low Jitter Design for 1.25 Gbps SerDes Receiver[J].Research & Progress of Solid State Electronics,2009,29(1). |
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| Authors: | LIU Wei XIAO Lei YANG Lianxing |
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| Affiliation: | State Key Laboratory of ASIC & System;Fudan University;Shanghai;201203;CHN |
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| Abstract: | Low jitter design of 1.25 Gbps SerDes(Serialize & De-serializer)receiver for Gigabit Ethernet is described. Frequency-aided dual-loop clock and data recovery circuit (CDR) is applied. FLL circuit is adopted to enhance the tracking range of CDR. A special phase detector based on three-state PFD is proposed here to extract clock information from 1.25 Gbps NRZ data stream,and drive a three-staged current-starving ring oscillator to generate the low jitter 1.25 GHz clock needed. Equalizer is also introduced for... |
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| Keywords: | low jitter clock and data recovery clock VCO dual loop phase detector SerDes |
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