数字高阶△-∑调制频率合成器的分析与实现

由小数分频频率合成器中相位累加器与数字一阶△-∑调制器的等效性出发，用ADS软件仿真证实了高阶数字△-∑调制对量化相位噪声的高通整型功能，从而有效地解决了小数分频的杂散问题。最后硬件电路实现了基于△-∑调制的小数分频跳频频率合成器，频率范围为590～1000MHz，在偏离主频10KHz时相噪优于-93．76dBc／Hz，频率分辨率可以小于100Hz，转换时间小于50μs，在跳频频率间隔1MHz时每秒可达2万跳。

Analysis and Realization of Fractional-N Frequency Synthesizer with a Digital High Order △-∑ Modulator

Based on the equivalence of noise-shaping function between the first order delta-sigma modulator and traditional phase accumulator of fractional-N frequency synthesizer, noise characteristics of the high order delta-sigma modulator is analyzed and experimentally verified. With the influence of the high order delta-sigma modulator, the spurious phase noise introduced by fractional-N division possesses of high-pass characteristics can be suppressed by the loop filter of the phase-lock-loop (PLL). A fractional-N frequency synthesizer with the high order delta-sigma modulator is realized using monolithic IC. The working frequency is between 590 to 1000MHz. The measured phase noise is lower than 93.76dBc/Hz at 10KHz offset. Ultra-small step size is 100 Hz or less with switching time less than 50ms, satisfying the requirement of most wireless communication systems.