PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element |
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Authors: | Pauls Greg Kalkur Thottam S |
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Affiliation: | Microelectronics Research Laboratories, Department of Electrical and Computer Engineering, University of Colorado, Colorado Springs, CO 80933-7150, USA. |
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Abstract: | Ferroelectric capacitors have steadily been integrated into semiconductor processes due to their potential as storage elements within memory devices. Polarization reversal within ferroelectric capacitors creates a high nonlinear dielectric constant along with a hysteresis profile. Due to these attributes, a phase-locked loop (PLL), when based on a ferroelectric capacitor, has the advantage of reduced cycle-to-cycle jitter. PLLs based on ferroelectric capacitors represent a new research area for reduction of oscillator jitter. |
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