A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM |
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| Authors: | Toyoshima H. Kuhara S. Takeda K. Nakamura K. Okamura H. Takada M. Suzuki H. Yoshida H. Yamazaki T. |
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| Affiliation: | Microelectron. Res. Labs., NEC Corp., Sagamihara ; |
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| Abstract: | A 0.3-μm 4-Mb BiCMOS SRAM with a 6-ns access time at a minimum supply voltage of 1.5 V has been developed. Circuit technologies contributing to the low-voltage, high-speed operations include: (1) boost-BiNMOS gates for address decoding circuits; (2) an optimized word-boost technique for a highly-resistive-load memory cell; (3) a stepped-down CML cascoded bipolar sense amplifier; (4) optimum boost-voltage detection circuits with dummies for boost-voltage generators |
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