RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique |
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| Affiliation: | 1. Electrical Engineering Department, United Arab Emirates University, Al-Ain 15551, UAE;2. Department of Electrical Engineering, Linkoping University, SE-581 83 Linkoping, Sweden;1. Department of Computer Science and Technology, Beijing University of Chemical Technology, No.15, Beisanhuan East Road, ChaoYang District, Beijing 100029, China;2. Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;3. Department of Electronic and Communication Engineering, School of Electrical and Electronic Engineering, North China Electric Power University, Baoding 071003, China;4. School of Computer and Information, Hefei University of Technology, Hefei 230009, China;1. School of Electrical and Computer Engineering, University of Tehran, Iran;2. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Iran;3. Department of Electrical Engineering-Systems, University of Southern California, USA;1. Department of Electrical and Electronic Engineering, Bogazici University, Istanbul, Turkey;2. IMSE, CSIC and University of Seville, Spain;1. Guangzhou Institute of Advanced Technology, CAS, China;2. Shenzhen Institute of Advanced Technology, CAS, China;3. The Chinese University of Hong Kong, China;4. University of Nevada, Las Vegas, United States;5. University of Turku, Finland;6. Royal Institute of Technology, Sweden |
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| Abstract: | The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a RF calibration scheme for DfT chain using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65 nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error due to process variation in DfT circuit can be reduced to 2.5% provided the input test stimuli is large in magnitude. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging. |
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| Keywords: | DfT On-chip RF detector RF BIST RF calibration RF DfT RF testing ANN application |
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