A new parallel hardware architecture for high-performance stereo matching calculation |
| |
| Affiliation: | Kwangwoon University, 447-1, Welgye-1Dong, Nowon-Gu, Seoul 139-701, Republic of Korea;Electrical Engineering Department of Universidade Federal do Espírito Santo, Av. Fernando Ferrari, Goiabeiras, 29060-900 Vitória, ES, Brazil;School of Engineering and Built Environment, Glasgow Caledonian University, Glasgow, Cowcaddens Road, UK;School of Engineering, Damghan University, Postal Code 3671641167, Damghan, Iran;Department of Computer Science and Applied Mathematics, Technical University of Denmark, Lyngby 2800, Denmark;Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, United States |
| |
| Abstract: | In this paper, we propose a hardware (H/W) architecture to find disparities for stereo matching in real time. After analyzing the arithmetic characteristic of stereo matching, we propose a new calculating method that reuses the intermediate results to minimize the calculation load and memory access. From this, we propose a stereo matching calculation cell and a new H/W architecture. Finally, we propose a new stereo matching processor. The implemented H/W can operate at the clock frequency of 250 MHz at least in the FPGA (field programmable gate array) environment and produce about 120 disparity images per second for HD stereo images. |
| |
| Keywords: | Stereo vision Stereo matching Architecture Disparity FPGA Memory bandwidth |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
