Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors |
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| Affiliation: | 1. E-SoC Lab. & Smart Computing Lab., Dept. of Computer Engineering, Hallym University, South Korea;2. Verimag Research Lab., University of Joseph Fourier, Grenoble, France;1. Institute for Applied Analysis and Numerical Simulation, University of Stuttgart, Pfaffenwaldring 57, 70569 Stuttgart, Germany;2. Fakultät für Mathematik (LS3), TU Dortmund, Vogelpothsweg 87, 44227 Dortmund, Germany;1. Ecole Normale Supérieure de Lyon, CNRS & INRIA, Lyon, France;2. University of Tennessee, Knoxville, TN 37996, USA;1. Science and Technology Facilities Council, Daresbury Laboratory, Sci-Tech Daresbury, Warrington WA4 4AD, United Kingdom;2. University of Zagreb, Faculty of Mechanical Engineering and Naval Architecture, Ivana Lučića 5, Zagreb 10000, Croatia;3. University of Zagreb, Faculty of Science, Department of Mathematics, Bijenička cesta 30, Zagreb 10000, Croatia |
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| Abstract: | Sparse matrix-vector multiplication (SpMV) is a central building block for scientific software and graph applications. Recently, heterogeneous processors composed of different types of cores attracted much attention because of their flexible core configuration and high energy efficiency. In this paper, we propose a compressed sparse row (CSR) format based SpMV algorithm utilizing both types of cores in a CPU–GPU heterogeneous processor. We first speculatively execute segmented sum operations on the GPU part of a heterogeneous processor and generate a possibly incorrect result. Then the CPU part of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement over the best existing CSR-based SpMV algorithms. |
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