Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications |
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Affiliation: | 1. PGMicro - UFRGS, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;2. IBM Research, Austin, TX, United States;3. PGMicro/PPGC - UFRGS, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil |
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Abstract: | This paper presents a novel multi-Gb/s multi-mode LDPC decoder architecture and efficient design techniques for gigabit wireless communications. An efficient dynamic and fixed column-shifting scheme is presented for multi-mode architectures. A novel low-complexity local switch is proposed to implement the dynamic and fixed column-shifting scheme. Furthermore, an efficient quantization method and the usage of a one?s-complement scheme instead of a two?s-complement scheme are explored. The proposed decoder achieves very high throughput with minimal area overhead. Post layout results using TSMC 65-nm CMOS technology shows much better throughput, as well as better area- and energy-efficiency, compared to other multi-mode LDPC decoders. |
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Keywords: | LDPC code Multi-mode decoder Gigabit 60-GHz 802 11ad Wireless communications |
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