Analysis of High-Speed GaAs Source-Coupled FET Logic Circuits

A source-coupled FET logic (SCFL) circuit is proposed for gigabit rate digital signaf processing. FET threshold voltage tolerance in the SCFL circuit and the SCFL circnit performance are presented. The speed of the SCFL gate depends on the operating region of the FET. For high-speed operation, FET's drain-to-source voltage fdgher than a pinchoff voltage has to be suppfied. The SCFL gate, which is composed of 1.5-pm gate-length FET's, showsthat the minimum propagation time is predicted to be 25 ps/gate. Mhimum rise time and fall time are expected to be S4 ps and 51 ps, respectively. Maximum RZ data rate is expected to be 5.6 Gb/s. The SCFL circnit is applicablefor high-speed dlgitaf sigmd processing.