ZnO片式压敏电阻厚膜中Cr_2O_3含量的优化(英文)

研究三氧化二铬(Cr2O3)对氧化锌(ZnO)片式压敏电阻厚膜物相结构、微观结构和电性能的影响。X衍射分析表明:Cr2O3降低Bi4Ti3O12相的分解温度,并最终影响陶瓷厚膜的致密度、晶粒尺寸及电性能。当烧结温度为880℃时,Cr2O3摩尔(下同)掺量为0.3%的陶瓷厚膜能够得到良好性能:体积密度ρv=5.52g/cm3,晶界势垒Φb=0.116eV,非线性系数α=24.8。研究烧结温度与片式压敏电阻微观结构和电性能的关系,Cr2O3掺量为0.3%的片式压敏电阻在880℃烧结时,能够获得最佳电性能:压敏电压V1mA=25V,α=23.6,漏电流Il=2.8μA。该片式压敏电阻的低烧结温度和高非线性在工业生产中具有很大优势。

OPTIMIZATION ON Cr2O3 CONTENT IN ZnO MULTILAYER CHIP VARISTOR THICK FILMS

Effects of Cr2O3 additive on phase transformation, microstructure and electrical properties of ZnO varistor thick films used for multilayer chip varistors (MLVs) were investigated. The X-ray diffraction analysis reveals that the Cr2O3 additive can reduce de-composion temperature of Bi4Ti3Oi2 phase, which in turn influences densification, average grain size and electrical properties of ZnO varistor films. The ceramic film with 0.3% (in mole, the same below) Cr2O3 sintered at 880 ℃ exhibits the best performances, with 5.52 g/cm3 in bulk density (ρv), 0.116 eV in barrier height (Φb), and 24.8 in nonlinear coefficient(α). In addition, the influences of sintering temperature on microstructure and electrical properties of ZnO MLVs were also studied. The MLVs with 0.3% Cr2O3 sintered at 880 ℃ gain the best electrical properties, with breakdown voltage (V1 mA), a and leakage current (I1) values at 25 V, 23.6, and 2.8 μA, respectively, which exhibits a high advantage for multilayer chip varistors industrial production.