| TTA结构数字信号协处理器数据Cache的设计与实现 |
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| 引用本文： | 姜晶菲,郭建军,戴葵,王志英.TTA结构数字信号协处理器数据Cache的设计与实现[J].计算机工程与应用,2006,42(33):8-10,19. |
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| 作者姓名： | 姜晶菲 郭建军 戴葵 王志英 |
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| 作者单位： | 国防科学技术大学,计算机学院,长沙,410073 |
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| 摘 要： | 论文分析了面向多媒体应用的TTA(TransportTriggeredArchitecture)微处理器的特点和访存要求,提出并设计实现了应用于此款微处理器、采用直接映象规则、写回和按写分配策略的4KB数据Cache,并在全系统环境下对其进行了模拟验证。实验结果说明数据Cache系统在降低命中时间和提高命中率两方面做到了良好的折中,命中时间与芯片流水线处理周期匹配,有效保证了全系统性能的发挥。
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| 关 键 词： | TTA 数据Cache 直接映象 写回 按写分配 |
| 文章编号： | 1002-8331（2006）33-0008-03 |
| 收稿时间： | 2006-09 |
| 修稿时间： | 2006-09 |
Design and Implement of Data Cache for Digital Signal Coprocessor Based on TTA |
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| JIANG Jing-fei,GUO Jian-jun,DAI Kui,WANG Zhi-ying.Design and Implement of Data Cache for Digital Signal Coprocessor Based on TTA[J].Computer Engineering and Applications,2006,42(33):8-10,19. |
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| Authors: | JIANG Jing-fei GUO Jian-jun DAI Kui WANG Zhi-ying |
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| Affiliation: | School of Computer,National University of Defense Technology,Changsha 410073,China |
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| Abstract: | The characteristics of Transport Triggered Architecture(TTA) have been analyzed.The excellent process ability of TTA pipeline gave high demands to the data cache.A 4 KB data cache system which used direct mapped principle,write back and write allocate strategies has been proposed and implemented.The data cache combined with the TTA pipeline and other function units compose the whole TTA microprocessor.The microprocessor has been simulated completely with real applications.The implementation results prove that the data cache in TTA microprocessor can achieve excellent trade-off for hit time and hit probability.The hit time can match the pipeline cycle and the high performance of the microprocessor is ensured. |
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| Keywords: | TTA |
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