| 低相噪锁相介质振荡器研究 |
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| 引用本文： | 宋学峰,何庆国.低相噪锁相介质振荡器研究[J].半导体技术,2010,35(11):1126-1129. |
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| 作者姓名： | 宋学峰 何庆国 |
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| 作者单位： | 中国电子科技集团公司,第十三研究所,石家庄,050051;中国电子科技集团公司,第十三研究所,石家庄,050051 |
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| 摘 要： | 针对高的相位噪声指标要求,对取样锁相介质振荡器进行了研究.通过相位噪声分析,明晰了采用介质振荡器与取样锁相技术降低相位噪声的机理,并分别对介质振荡器与锁相环路进行了设计.设计中,应用HFSS与ADS对介质振荡器进行了联合仿真,体现了计算机辅助设计的优势.最终研制出17 GHz锁相介质振荡器,测试结果为:输出功率13.1 dBm;杂波抑制>70 dB;谐波抑制>25 dB; 相位噪声为-105 dBc/Hz@1 kHz,-106 dBc/Hz@10 kHz,-111 dBc/Hz@100 kHz,-129 dBc/Hz@1 MHz.
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| 关 键 词： | 相位噪声 介质振荡器 取样锁相环 联合仿真 计算机辅助设计 |
Study of Low Phase Noise Locking Phase Oscillators with Dielectric Resonators |
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| Song Xuefeng,He Qingguo.Study of Low Phase Noise Locking Phase Oscillators with Dielectric Resonators[J].Semiconductor Technology,2010,35(11):1126-1129. |
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| Authors: | Song Xuefeng He Qingguo |
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| Affiliation: | Song Xuefeng,He Qingguo(The 13th Research Institute,CETC,Shijiazhuang 050051,China) |
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| Abstract: | The low phase noise locking phase oscillator with the dielectric resonator was studied for the requirement of low phase noise.The theory of reducing phase noise was ascertained by the DRO and sampling phase-lacked teckniques after studying the concept of the phase noise in detail,then the DRO and the sampling phase-locked circuit were designed.A co-simulation of HFSS and ADS was used in the design of DRO and had a good effect on CDA. A 17 GHz locking phase oscillator with the dielectric resonator was develo... |
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| Keywords: | phase noise DRO sampling phase-locked loop co-simulation CAD |
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