A Signed Array Multiplier with Bypassing Logic

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.