FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System |
| |
Authors: | Jeich Mar Chi-Cheng Kuo Shih-Hao Chou |
| |
Affiliation: | (1) Department of Communications Engineering, Yuan-Ze University, 135 Yuan-Tung Road, Jungli, Taoyuan, 320, Taiwan, Republic of China |
| |
Abstract: | Based on software defined radio (SDR) architecture, this paper develops a reconfigurable CORDIC vectoring module (CVM) and
CORDIC rotation module (CRM) in FPGA to implement the carrier frequency offset (CFO) estimation and compensation circuits
of an orthogonal frequency division multiplexing (OFDM) system. The experimental results show that the proposed SDR-pipelined
architecture can save power and hardware resource compared with conventional pipelined architecture, because the designed
CVM and CRM modules can be reused in the processing modules of CFO estimation and compensation circuit. The performance trade-off
for CVM and CRM implemented with different quantized float number in FPGA is presented. Furthermore, the hardware reconfiguration
function of CVM and CRM is also validated. |
| |
Keywords: | |
本文献已被 SpringerLink 等数据库收录! |
|