Design of CMOS circuits for stuck-open fault testability |
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Authors: | Jayasumana A.P. Malaiya Y.K. Rajsuman R. |
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Affiliation: | Colorado State Univ., Fort Collins, CO; |
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Abstract: | A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes |
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