PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design |
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Authors: | N Wang A Sanusi P Y Zhao M Elgamel M A Bayoumi |
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Affiliation: | (1) Department of Electrical and Computer Engineering, WVU Institute of Technology, 405 Fayette Pike, Montgomery, WV 25136, USA;(2) Department of Mathematics and Computer Science, Chapman University, One University Drive, Orange, CA 92866, USA;(3) The Center for Advanced Computer Studies, University of Louisiana at Lafayette, 301 East Lewis Street, Lafayette, LA 70503, USA |
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Abstract: | With the de facto transformation of technology into nano-technology, more and more functional components can be embedded on
a single silicon die, thus enabling high degree pipelining operations such as those required for multimedia applications.
In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively
complicated systems with multiple processors, on-chip memories, standard peripherals, and other functional blocks. The communication
between these IP blocks is becoming the dominant critical system path and performance bottleneck of system-on-chip designs.
Network-on-chip architectures, such as Virtual Channel (2004), Black-bus (2004), Pirate (2004), AEthereal (2005), and VICHAR (2006) architectures, emerged as promising solutions for future system-on-chip communication architecture
designs. However, these existing architectures all suffer from certain problems, including high area cost and communication
latency and/or low network throughput. This paper presents a novel network-on-chip architecture, Pipelining Multi-channel
Central Caching, to address the shortcomings of the existing architectures. By embedding a central cache into every switch
of the network, blocked head packets can be removed from the input buffers and stored in the caches temporally, thus alleviating
the effect of head-of-line and deadlock problems and achieving higher network throughput and lower communication latency without
paying the price of higher area cost. Experimental results showed that the proposed architecture exhibits both hardware simplicity
and system performance improvement compared to the existing network-on-chip architectures. |
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