ON SHORTENING TEST SEQUENCE LENGTH FOR SIGNATURE ANALYZER

Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.

On shortening test sequence length for signature analyzer

Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.