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基于FPGA的数字日历设计
引用本文:刘娟花,厉 谨. 基于FPGA的数字日历设计[J]. 现代电子技术, 2014, 0(3): 137-140
作者姓名:刘娟花  厉 谨
作者单位:西安工程大学 电子信息学院,陕西 西安710048
基金项目:西安工程大学大学生创业创新项目(2012030427)
摘    要:介绍了一种基于FPGA的数字日历设计方案,采用VHDL语言编程设计了一个具有年、月、日、星期、时、分、秒计时显示功能,时间调整功能和整点报时功能的数字日历。采用VHDL和原理图相结合的设计输入方式,在QuartusⅡ开发环境下完成设计、编译和仿真,并下载到FPGA芯片EP1C3T144-3上进行结果验证。结果表明:该设计方案切实可行,对FPGA的应用和数字日历的设计具有一定参考价值。

关 键 词:数字日历  VHDL  FPGA  QuartusⅡ

Design of digital calendar based on FPGA
LIU Juan-hua,LI Jin. Design of digital calendar based on FPGA[J]. Modern Electronic Technique, 2014, 0(3): 137-140
Authors:LIU Juan-hua  LI Jin
Affiliation:(Faeuhy of Electronic Information, Xi' an Polytechnic University, Xi' an 710048, China)
Abstract:A design scheme of digital calendar based on FPGA is introduced. VHDL programming language is used to de-sign the digital calendar,which has functions of displaying the year,month,day,week,hour,minute,second,time adjust-ment and the Hourly chime. The input method of the scheme is in combination VHDL and block diagram. The design,compiling and simulation are completed under Quartus Ⅱ development environment. The designed file is accomplished and downloaded into FPGA chip EP1C3T144-3 to verify the results. The experiment results verify that the design scheme is workable,and can pro-vide references for the application of FPGA and the design of digital calendar.
Keywords:digital calendar  VHDL  FPGA  Quartus Ⅱ
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