Statistics of Grain Boundaries in Polysilicon |
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| Authors: | Watanabe H. |
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| Affiliation: | Adv. LSI Technol. Lab., Toshiba Corp., Yokohama; |
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| Abstract: | A nanometer-scale variation of grain boundary locations in gate polysilicon is investigated in detail based on the assumption that the arrangement of grain boundaries obeys Poisson distribution. The statistics of grain boundaries described here reveals a relation between nanoscopic location and the arrangement of grain boundaries, which implies fluctuation in transistor characteristics of 45-nm and beyond MOSFETs |
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