首页 | 本学科首页   官方微博 | 高级检索  
     

多通道像素并行输出哈特曼波前传感器的实时质心运算流水线架构设计
引用本文:宋璐,王少白. 多通道像素并行输出哈特曼波前传感器的实时质心运算流水线架构设计[J]. 广东电脑与电讯, 2016, 1(4): 69-71
作者姓名:宋璐  王少白
作者单位:河南科技大学,河南洛阳471023;2.中国航空工业集团公司洛阳电光设备研究所
摘    要:基于可编程逻辑器件,设计了一种针对横向多通道像素并行输出特点的哈特曼波前传感器的实时质心运算流水线架构。该架构由乘法器单元、累加单元和除法单元组成,各个单元内运算器的数目可根据输出通道数和输出像素顺序自由配置。对于一帧图像的质心运算,经过该架构处理后延时仅为对最后输出的一个像素处理所需时间。仿真结果表明,对于以80MHz 的时钟频率,横向8 个像素并行输出的哈特曼波前传感器,其运算延时不超过0.5μs。

关 键 词:质心运算  并行像素输出  可编程逻辑器件  哈特曼波前传感器  

Pipeline Structure Design for Real-time Centroid Calculation of HartmannWavefrontSensor with Parallel Multi-channel Pixel Output
Song Lu,Wang Shaobai. Pipeline Structure Design for Real-time Centroid Calculation of HartmannWavefrontSensor with Parallel Multi-channel Pixel Output[J]. Computer & Telecommunication, 2016, 1(4): 69-71
Authors:Song Lu  Wang Shaobai
Abstract:In this paper, a real-time pipeline centroid calculating structure based on programmable logic devices is designed forHartmann wavefront sensor with horizontal multi-channel pixel output. The structure is composed of multiplier groups, accumulationcells and dividers. The cells are designed according to the number of output channels and the output pixels’sequence. The centroidcalculation latency in one frame is only the calculation time needed for the pixels output at the last pixel clock. In the simulation,when output channels’number is 8 and pixels output at 80MHz clock, centroid calculation latency is less than 0.5μs.
Keywords:centroid computation  parallel pixel output  programmable logic devices  Hartmann wavefront sensor  
点击此处可从《广东电脑与电讯》浏览原始摘要信息
点击此处可从《广东电脑与电讯》下载全文
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号