Integrated Circuit Implementation of a Compact Discrete-Time Chaos Generator

A discrete-time chaos generator implemented with two nonlinear circuit cells has been fabricated in a 0.6 μm CMOS technology. Each cell is creating a function (map) which allows a chaos signal to be generated. Measurements of the chip were performed with a supply voltage of 5 V, up to a frequency of 2.5 MHz. A bifurcation diagram of the circuit and the Lyapunov exponent calculation are presented. The size of the generator layout (without the switches) is 32 × 19 μ m which makes it suitable for applications where many chaos signal generators are required on a single chip. Dan Juncu received the B.S. and M.Sc. degrees in Electrical and Electronics Engineering from the Technical University, Iasi, Romania in 1997 and 1998, respectively, and the Ph.D. degree in Electronics from UMIST, Manchester, UK in 2003. For his Ph.D. he did research on sensor interfaces for gas sensing devices; after that, he worked on RF IC on a new SiGe technology. In 2004 he joined Cambridge Consultants, Cambridge, UK. His current interests are in the area of switched capacitor filtering and computation, and sensor interfacing. Mandana Rafiei-Naeini received the B.Sc. degree in Electrical Engineering (majoring in Electronics) from Islamic Azad University of Tehran, Iran, in 2001 and the M.Sc. degree with distinction in Electronic Instrumentation Systems from University of Manchester in 2004. She is currently studying towards her Ph.D. degree in the School of Electrical and Electronic Engineering at The University of Manchester, working on clinical electrical impedance tomography systems for brain function imaging. She is a student member of IEE and IEEE. Piotr Dudek received his mgr in ż degree in electronic engineering from the Technical University of Gdańsk, Poland in 1997 and the M.Sc. and Ph.D. degrees from the University of Manchester Institute of Science and Technology (UMIST), Manchester, UK, in 1996 and 2000, respectively. He worked as a Research Associate at UMIST until 2002. Currently, he is a Lecturer in Integrated Circuit Engineering at The University of Manchester. His research interests are in analogue and mixed-mode VLSI circuits, smart sensors, machine vision, massively parallel processors, cellular arrays, bio-inspired engineering and spiking neural networks.