ESD protection techniques for high frequency integrated circuits

The high frequency performance characteristics of integrated circuits (ICs) can be severely degraded by the addition of electrostatic discharge (ESD) protection networks on input or output pins. However, without protection networks ICs can be extremely sensitive to ESD. This paper will present a review of a number of techniques that have been used to protect ICs without significantly degrading their AC operating performance. Experimental results showing improved ESD performance are included for some of these techniques. Although the emphasis of the paper will be on silicon based circuits, III-V compounds will also be addressed.