| 基于USB3.0协议的PC与FPGA通信系统的设计 |
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| 引用本文： | 杨翠翠,朱向东,李帆.基于USB3.0协议的PC与FPGA通信系统的设计[J].电子科技,2014,27(10):136-138. |
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| 作者姓名： | 杨翠翠 朱向东 李帆 |
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| 作者单位： | (西安科技大学 电气与控制工程学院,陕西 西安 710054) |
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| 摘 要： | 针对USB2.0在高速数据采集系统中带宽局限问题,设计了一款基于USB3.0总线的高速数据采集接口系统。通过对USB3.0的接口硬件系统、设备固件以及SLAVE FIFO与FPGA接口读写操作的设计,并经过实验测试,USB3.0硬件传输速度可达260 MByte·s-1,连续数据采集传输速率可达100 MByte·s-1且数据保持稳定。
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| 关 键 词： | FPGA USB3.0固件 SLAVE FIFO 数据通信 |
Design of Data Transmission Between PC and FPGA Based on USB3.0 Bus Protocol |
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| YANG Cuicui,ZHU Xiangdong,LI Fan.Design of Data Transmission Between PC and FPGA Based on USB3.0 Bus Protocol[J].Electronic Science and Technology,2014,27(10):136-138. |
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| Authors: | YANG Cuicui ZHU Xiangdong LI Fan |
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| Affiliation: | (School of Electrical and Control Engineering,Xi'an University of Science & Technology,Xi'an 710054,China) |
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| Abstract: | A high-speed data acquisition system is designed to solve the problems in bandwidth limitation. The design consists of the USB3. 0 Interface System,USB3. 0 Firmware and R /W Operation of SLAVE FIFO to FPGA.Test results show that the USB3. 0 transmission rate reaches 260 MByte·s-1with a stable data transmission speed of Continuous Data Acquisition System up to 100 MByte·s-1. |
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| Keywords: | FPGA USB3 0 SLAVE FIFO data transmission |
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